1. Field of Invention
The present invention relates to a method of fabricating a semiconductor device. More particularly, the present invention relates to a fabrication method of a gate structure so as to reduce stress production.
2. Description of Related Art
In a high integration semiconductor process, a metal oxide semiconductor transistor, known as MOS transistor in short, has been adopted to replace the role played by the conventional bipolar transistor in conducting current in the semiconductor device. The MOS transistor generally comprises of a gate structure to which the input signal is normally applied, and a source/drain region, across which the output voltage is developed, and through which the output current flows.
A conventional fabrication process for the gate structure includes forming a gate oxide layer on an active region of a substrate defined by isolation structures. A gate stack comprising of a polysilicon layer, a metal silicide layer, and a nitride layer was hen formed on the gate oxide layer. The process continued by forming a buffer oxide layer on sidewalls of the gate stack, and forming a nitride spacer on sidewalls of the buffer oxide layer. FIGS. 1A through 1E illustrate the conventional fabrication process for the gate structure and some problems created when the buffer oxide layer was formed using different oxidation methods.
Referring to FIG. 1A, a substrate 100 is provided with an active region (not shown) defined by isolation structures 102 in the substrate 100. A gate oxide layer 104 is then grown on the substrate 100, followed by formation of a gate stack 111. The gate stack 111 comprises of a doped polysilicon layer 106 to provide an electrical conduction, a metal silicide layer 108 to enhance a transmission speed, and a nitride layer 110 for passivation. The method for forming the gate stack 111 includes depositing in sequence the doped polysilicon layer 106, the metal silicide layer 108, and the nitride layer 110 on the gate oxide layer 104, followed by patterning the three layers to obtain the gate stack 111 on the active region.
Referring to FIG. 1B, a buffer oxide layer 112a is formed to cover the gate stack 111 and the gate oxide layer 104. The buffer oxide layer 112a is known to reduce a stress induced by a nitride spacer (not shown), and one common approach for forming the buffer oxide layer 112a includes low-pressure chemical vapor deposition (LPCVD).
Referring to FIG. 1C, another nitride layer (not shown) for forming a nitride spacer 114 is formed on the buffer oxide layer 112a. The nitride spacer 114 is formed using an etch-back process to remove the excess nitride layer. An etch-back process is further performed to remove the excess buffer oxide layer 112a on the nitride layer 110. A lightly doped drain (LDD) implantation is performed to dope ions into the substrate 100 for forming a source/drain region 116. However, the buffer oxide layer 112a formed as such creates a buffer oxide breakthrough problem when a self-aligned contact (SAC) opening is subsequently formed by etching. After forming a silicon oxide layer 118 for insulation, a large portion the buffer oxide layer 112a is also removed together with a part of the silicon oxide layer 118, as shown in FIG. 1C. This creates a notch that exposes the conductive material in the gate stack to a metal layer deposited in the subsequent process. As a result, an electrical problem, such as short circuit occurs in the fabrication process.
The process step described in FIG. 1C is different from FIG. 1D and FIG. 1E only in terms of the oxidation approach for forming the buffer oxide layer, therefore similar process steps will not be described further herein. Referring to FIG. 1D, the buffer oxide layer 112b is formed on the gate oxide layer 104 and sidewalls of the metal silicide layer 108 and the polysilicon layer 106. The buffer oxide layer 112b is formed by rapid thermal oxidation (RTO), so that the buffer oxide layer 112b formed on the gate oxide layer 104 is thicker than the buffer oxide layer 112b formed on the sidewalls of the metal silicide layer 108 and the polysilicon layer 106. However, the buffer oxide layer 112b formed by RTO usually requires conditions, such as high temperature and short duration, which conditions would produce a stress that degrades the gate oxide layer. And besides the problem of gate oxide degradation, the fabrication process that includes RTO also incurs a high thermal budget. FIG. 1E, illustrates another approach for forming the buffer oxide layer 112c, where the buffer oxide layer 112c is grown by thin oxidation in a furnace (not shown). This method of oxidation inevitably creates problems such as oxide encroachment, where a part of buffer oxide layer 112c grows into the polysilicon layer 106 to damage the gate stack 111. According to this oxidation, the buffer oxide layer 112c grown on the sidewall of the gate stack 111 is thicker. As a result, this reduces the critical dimension (CD) and deteriorates the refresh time of the semiconductor device.